The present invention relates to a semiconductor device having an arrangement of molding a semiconductor chip with resin and a manufacturing method of the same.
Advances of electronic components in size and thickness reduction technologies in the past few years have made it possible to provide electronic components having highly improved performances, specifically in the field of semiconductor devices such as memories. This tendency will lead to the need of developing semiconductor devices which are compact in size, thin in thickness, low in cost, reliable in performance, and suitable for high-density packaging.
The package of semiconductor devices, used to be made of ceramic, are being rapidly changed to the resin type to realize the above requirements. Among them, surface mounting type resin molding packages have been increasing their demands since they are advantageous in providing higher mounting density compared with their competitive insertion type packages. The surface mounting type semiconductor packages are generally classified into some specific groups, such as QFP, SOP and SOJ, depending on their detailed constructions.
A semiconductor device having an SOP-type resin package will be explained hereinafter as a first conventional semiconductor device with reference to FIG. 21.
FIG. 21 is a cross-sectional view showing the first conventional semiconductor device. In FIG. 21, a reference numeral 21 represents a semiconductor chip, a reference numeral 22 represents a resin package, a reference numeral 23 represents a connecting lead made of 42 alloy or copper, a reference numeral 25 represents an aluminum electrode, a reference numeral 26 represents a bonding wire made of Au, a reference numeral 27 represents a die pad, and a reference numeral 28 represents a die bonding paste such as Ag paste.
The semiconductor chip 21 is fixed to the die pad 27 by means of the die bonding paste 28. An internal lead 23a of the connecting lead 23 is applied a thin coating of Ag or the like. The aluminum electrode 25 of the semiconductor chip 21 is connected to the internal lead 23a of the connecting lead 23 via the bonding wire 26. The package resin 22 seals the semiconductor chip 21, the bonding wire 26, the die pad 27 and the internal lead 23a therein. An external lead 23b of the connecting lead 23 extends out of the package 22.
In the field of general purpose memory devices, an outer configuration of the package, having a small size regulated by the industrial standards such as JEDEC and EIAJ, tends to cause a very severe problem of how such a small package can accommodate a newly developed semiconductor chip having a capacity rapidly expanded every generation.
Proposed to solve such a problem is an LOG (Lead On Ship) arrangement advantageous to install a large area semiconductor chip into a small-sized package.
With reference to FIG. 22, a second conventional semiconductor device having an LOG arrangement will be explained.
FIG. 22 is a cross-sectional view showing the second conventional semiconductor device. In FIG. 22, a reference numeral 21 represents a semiconductor chip, a reference numeral 22 represents a resin package, a reference numeral 23 represents a connecting lead, a reference numeral 25 represents an aluminum electrode, a reference numeral 26 represents a bonding wire, and a reference numeral 29 represents a polyimide tape. As shown in FIG. 22, an internal lead 23a of the connecting lead 23 is disposed above the main surface of the semiconductor chip 21.
The polyimide tape 29 has both surfaces on which thermoplastic adhesive material such as polyether amide is coated. The internal lead 23a is connected to the main surface of the semiconductor chip 21 by means of this adhesive material. As the polyimide tape 29 of the second conventional semiconductor device serves as a means of connecting the semiconductor chip 21 and the connecting lead 23 in this manner, the die pad 27 is no longer necessary.
Thus, the semiconductor device having an LOC arrangement allows the internal lead 23a of the connecting lead 23 to extend above the main surface of the semiconductor chip 21, so that the internal lead 23a is connected to the aluminum electrode 25 by means of the bonding wire 26. Accordingly, it becomes possible to reduce the unuseful space around the semiconductor chip 21, thereby enabling the large-area semiconductor chip 21 to be housed in the small-sized package 22.
However, such a semiconductor device having an LOC arrangement is inherently disadvantageous in that the package has a tall height. For the reduction of the height of the package, Unexamined Japanese Patent Application No. HEI 5235249/1993 discloses an improved semiconductor device having an arrangement shown in FIG. 23.
Hereinafter, a third conventional semiconductor device will be explained with reference to FIG. 23. In FIG. 23, a reference numeral 21 represents a semiconductor chip, a reference numeral 22 represents a package, a reference numeral 23 represents a connecting lead, a reference numeral 25 represents an aluminum electrode, a reference numeral 26 represents a bonding wire, and a reference numeral 30 represents a bus bar for electric power supply. As shown in FIG. 23, the bus bar 30 extends along the side surface of the semiconductor chip 21 so that the bus bar 30 is connected through a film with the semiconductor chip 21. Thus, it becomes possible to omit the die pad 27 shown in FIG. 21 and the polyimide 29 shown in FIG. 22.
However, the above-described second conventional semiconductor device has the following problems:
(1) Presence of the polyimide tape having high hygroscopicity causes moisture absorbed in the polyimide tape to vaporize during solder reflowing operation; therefore, cracks and voids will be easily caused in the semiconductor device. PA1 (2) Using the polyimide tape having such high hygroscopicity for connecting the internal leads tends to cause leakage between the connecting leads due to hygroscopicity. PA1 (3) A lead frame with a polyimide tape increases the production cost. PA1 (4) A process of setting a semiconductor chip into the lead frame requires a thermocompression bonding between the semiconductor chip and the lead frame by means of a 300-400.degree. C. high-temperature tool to melt the thermoplastic adhesive material coated on both surfaces of the polyimide tape to connect the semiconductor chip with the internal leads. Therefore, the semiconductor chip is possibly damaged by load and heat of the heating tool. PA1 (1) A process of setting the semiconductor chip into a clearance between two bus bars extending in parallel with each other is not easy to carry out. PA1 (2) Heat of sealing resin acts to thermally expand both the semiconductor chip and the lead frame. Difference of thermal expansion between the semiconductor chip and the lead frame will possibly damage the semiconductor chip by the compression force given from the lead frame. PA1 (3) Layout of the bus bar extending along the side surface of the semiconductor chip necessarily locates the distal end of the internal lead outside the bus bar; therefore, the LOC arrangement cannot be employed in this third conventional semiconductor device.
The third conventional semiconductor device has the following problems: